Description
Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution for some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.
References8
- intel.com/content/www/us/en/security-center/advisory/intel-sa-0…
- www.openwall.com/lists/oss-security/2025/05/12/5
- xenbits.xen.org/xsa/advisory-469.html
- lists.debian.org/debian-lts-announce/2025/05/msg00021.html
- lists.debian.org/debian-lts-announce/2025/08/msg00010.html
- lists.debian.org/debian-lts-announce/2025/10/msg00007.html
- cert-portal.siemens.com/productcert/html/ssa-019113.html
- cert-portal.siemens.com/productcert/html/ssa-457936.html
Metrics
- CVSS 3.1
-
5.6
MEDIUM
Score source: CNA
CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:C/C:H/I:N/A:N - CVSS 4.0
-
5.7
MEDIUM
Score source: CNA
CVSS:4.0/AV:L/AC:H/AT:P/PR:L/UI:N/VC:H/VI:N/VA:N/SC:N/SI:N/SA:N/E:X/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:X/R:X/V:X/RE:X/U:X - EPSS — exploit probability
- 0% percentile: 37 · as of 7 November 2026
Could this be exploited in your environment?
A patch closes the known hole. A penetration test shows what an attacker can still reach — with proof.